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Careers

You will have an opportunity to work with an excellent and dedicated team of professionals working towards changing the future of electronic design and testing ...

We are actively looking for:

Senior ASIC Verification Engineers
Senior Design Engineers
Software Engineer
ASIC Design Verification
FPGA Design
Circuit Design
Member Technical Staff
Technical Design Manager
Systems Administrator
Design For Test
Senior Software Engineer
Design Verification Engineer

Attention Employment Agencies:
Thank you for your interest in PERFECTUS Technology. At this time we are not accepting unsolicited resumes from outside agencies. All unsolicited resumes sent to us will be considered our property. If you are interested in providing us with your company information for service consideration, please note "Employment Agency" in the subject line and email: careers@perfectus.com

Senior ASIC Verification Engineers (Multiple Positions) (Job Code – SVE)

  • 8+ years of industry experience in SOC/ASIC verification.
  • Strong experience in Ethernet switch verification
  • Functional verification experience with large and complex chips.
  • Experience in test methodologies, test plan, regression, directed and random tests and test bench development
  • Knowledge of logic design background is a plus
  • Proficient in Verilog (PLI), C++, Perl.
  • Experience with formal verification tools.
  • Good knowledge of networking chip verification.
  • Masters degree in EE or CS from a reputable engineering institution.
  • Email your resume to careers@perfectus.com with Job Code – SVE in the subject line.

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Senior Design Engineers (Multiple Positions) (Job Code – SDE)

  • 8+ years of industry experience in ASIC verification.
  • Experience with large and complex chip designs.
  • Knowledge of logic design, state-machines, memory and FIFO designs.
  • Proficient in Verilog HDL, PLI.
  • Proficient in synthesis tools (Synopsys or Ambit).
  • Experience and familiarity with backend tools.
  • Experience with timing closure issues for large and complex chips.
  • Good knowledge of networking systems.
  • Masters degree in EE or CS from a reputable engineering institution.
  • Email your resume to careers@perfectus.com with Job Code – SDE in the subject line.

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Software Engineer(Job Code – SE)

  • B.S or equiv. degree and 5 years experience.
  • Job entails and requires experience in Java nad its major components.
  • Development exp on voice messaging applications using VXML, DTMF, TTS and voice browsers.
  • Strong experience in J2EE presentation-tier technologies including  JSP, JSTL, custom tags and XML.
  • Extensive knowledge in using design patterns and standard algorithms.
  • Experience in Spring MVC/Web Flow, IOC, AOP with Hibernate is necessary.
  • Working knowledge of AJAX with advanced JavaScript, DOM, DHTML, XSLT and CSS.
  • Working experience with Java IDE Eclipse using SVN / Clearcase as repository tool.
  • Good knowledge in using tools like Ant/Maven, Junit, Selenium.
  • Extensive usage of tools including Rational Rose, MS Visio, Cleartool/Version ONE.
  • Advanced knowledge of Linux/Unix environment is preferred.
  • Wireless application development experience using WML/WAP will be an added advantage.
  • Ability to work independently and effectively in a fast-paced environment
  • Email your resume to careers@perfectus.com with Job Code – SSE in the subject line.

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ASIC Design Verification (Job Code - VE)

  • Responsible for design verification at chip level ensuring design meets architectural / system requirements.
  • Responsible for developing test environment, test bench development, bus protocol checking, transaction level checking and performance modeling.
  • Experience in advanced verification languages such as VERA, Specman & System C is desrirable.
  • 3-5 years of solid design verification experience required.
  • Min Educational Requirements BS in EE. MS in EE preferred.
  • Email your resume to careers@perfectus.com with Job Code – VE in the subject line.

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FPGA Design (Job Code- FPGA)

  • Responsible for high-speed multimillion-gate and multi-clock domain FPGA designs.
  • Experience in translation of hardware requirements into a proven, scalable, system architecture and design.
  • Responsible for designing from initial specifications to silicon.
  • Experience with Xilinx / Altera FPGAs, embedded multi-processor interface architectures, Verilog/VHDL RTL design, verification, FPGA synthesis/timing, lab validation planning/execution.
  • Min Educational Requirements BS in EE. MS in EE preferred.
  • Email your resume to careers@perfectus.com with Job Code – FPGA in the subject line.

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Circuit Design (Job Code - DE)

  • In depth knowledge of full custom (transistor level) CMOS VLSI circuit layout techniques.
  • Ability to create high density, high performance CMOS layouts and understand tiled layout.
  • Knowledge of CAD tools for IC layout, design rule checking and layout vs. schematic comparison (LVS).
  • Experience using Cadence & Mentor digital / analog design tool suite, Simulators - Avant! H SPICE / Mentor ELDO simulator / NASDA HSIM & verification tools like Mentor Calibre & Cadence Dracula. Knowledge in developing behavioral models for design sub-blocks / digital circuits.
  • Min Educational Requirements BS in EE. MS in EE preferred.
  • Email your resume to careers@perfectus.com with Job Code – DE in the subject line.

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Member Technical Staff- MTS (Job Code - MTS)

  • B.S. or equiv. degree and 5 years experience.
  • Job entails and requires experience in: IP core development; RTL coding; verification using C, C++, Verilog HDL.
  • Synthesis, Static timing analysis and DFT.
  • Developing verification strategies and test plans;
  • Any of the following protocols/domains: Fibrechannel, SATA, USB and PCI.
  • Relocation within USA Possible.
  • Email your resume to careers@perfectus.com with Job Code – MTS in the subject line.

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Technical Design Manager- TDM (Job Code - TDM)

  • M.S or equiv. degree and 3 years experience
  • Job entails and requires experience in Design and verification using C/C++, Verilog HDL, VCS, Pearl timing analysis, Cadence Buildgates.
  • Implementing and mapping of PCI-Express core interface on Xilinx Virtex-II FPGA.
  • Synthesizing using synplify tool, any two of the following protocols/domains:
    RapidIO, Gigabit Ethernet and SONET
  • Relocation within USA Possible
  • Email your resume to careers@perfectus.com with Job Code – TDM in the subject line.

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Systems Administrator - SA (Job Code - SA)

  • 5 years experience.
  • Job entails & requires experience in: Installing and Configuring, Sonicwall Pro Firewall with VPN connectivity; installing & maintaining desktops with Windows, Linux & Sun Solaris.
  • Implementing network security; designing the network topology, and cabling using CAT5 cabling.
  • Configure DNS, WINS, fax, and print services on servers
  • Creating and Maintaining NIS domain in Sun Solaris environment
  • Installing DB server on Dell Poweredge 6300 & Application Server with MSSQL/Cold Fusion/IIS/ on Poweredge 2400 servers
  • Email your resume to careers@perfectus.com with Job Code – SA in the subject line.

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Design For Test - DFT (Job Code - DFT)

  • Experience with the design and implementation of test methodologies for large, complex SoCs.
  • Capable of resolving scan issue in complex multi-clock domain designs, developing DFT strategies for complex System-On-Chip designs, generate & integrate Memory BIST, JTAG, SCAN/ATPG.
  • Expert in analysis of fault coverage, delay fault, and enhancements.
  • Experience in developing and running scan insertion scripts, performing ATPG simulation & analyzing results.
  • Expertise in Mentor / Synopsys DFT tools and debug skills in a Verilog design environment.
  • Experience with static timing analysis (STA) & formal verification is desirable.
  • Proficiency in common UNIX scripting languages (perl, tcl, csh, sh).
  • Email your resume to careers@perfectus.com with Job Code – DFT in the subject line.

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Senior Software Engineer- SE (Job Code - SSE)

  • Masters degree with 1 year experience or a bachelors degree with 6 years experience
  • Job entails and requires experience in working with Oracle, Java, C++, TIBCO Products including Designer, Business Works, XMLCanon, Administrator and Rendezvous, and Unix.
  • Experience must include analysis, design and development of software applications.
  • Relocation in within USA possible.
  • Email your resume to careers@perfectus.com with Job Code – SSE in the subject line.

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Design Verification Engineer - DVE (Job Code - DVE)

  • Master’s with 1 year experience or Bachelor’s with 6 years experience
  • Developing Assertion Based Verification packages and tools
  • Assertion test plans for the various protocols
  • Full chip verification using Verilog, C, Object Oriented Programming
  • Silicon/Board debug
  • Working with PCIE, PSL, System Verilog, OVL, Verilog, PERL, NCVerilog and Modelsim
  • Email your resume to careers@perfectus.com with Job Code DVE in the subject line

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