Perfectus Corporation

SOC & ASIC Concept to Product

Perfectus offers full-service support for SOC and ASIC designs, from customer’s specification to GDSII with full verification. With ever-increasing emphasis on faster, better quality and lower cost in today's multi-million gate complex SOC and ASIC designs, Perfectus provides service expertise in numerous areas to convert design specifications to working silicon in short time.

Our areas of expertise include:

Architecture and Design
Design Verification
Design Methodology & Flow
Physical Design & Verification
Circuit Design
DFT Architecture and Design

Our Architecture and Design services include:

Architectural specification & Modelling
Micro-architecture design
RTL coding
Design Partitioning and implementation
Model Development for simulation
Synthesis and chip integration
Formal verification
Static-timing analysis
Static-timing analysis

Design Verification :

Test plan development
Verification, Test & Regression environment setup
Directed test generation
Directed and focused Random test generation
Model Development for simulation
Functional & Code Coverage Analysis
Gate Level Verification with and without timing
Test Vector Generation

Design Methodology & Flow :

Design Methodology Consulting
EDA Tools Flow Setup
SoC Design Flow setup
IP Vendor Qualification

Physical Design & Verification :

Physical synthesis
Hierarchical floor planning and design partitioning
Directed test generation
Place & Route
Physical optimization and timing closure
Signal and power integrity assurance
Physical verification (Parasitic Extraction, Post-Layout Timing Verification)

Circuit Design :

Custom Circuit Design
Schematic Entry & Circuit verification
Cell Layout Design and Layout Verification
Characterization

DFT :

Design for Testability
Integration of Scan and BIST
Test vector integration and management
Chip-level test vector derivation
Scan - Full, partial and boundary
Logic and memory BIST
Automated test pattern generation
Fault grading of functional vectors
JTAG