SMBUS Verification IP

Highlights

• Compliant to SMBus 2.0 specification
• Generates and drives bus traffic as a SMBus 2.0 Master or SMBus 2.0 Host
• Responds to transactions as a SMBus 2.0 Slave which can be configured either to work as SMBus 2.0 slave or memory compatible with two wire serial EEPROM
• SMBus 2.0 Master has capability to generate commands and user configurable knobs
• Knobs to configure SMBus 2.0 transactions
• SMBus Verification IP has a stand alone SMBus 2.0 checker which checks and reports for all protocol violations
• Stand alone SMBus 2.0 checker also generates a coverage report on the check points being excercised by the testcases
• SMBus 2.0 Master & SMBus 2.0 slave has ability to inject Packet Error Checking (PEC) error & multiple protocol errors
• SMBus 2.0 Master & SMBus 2.0 slave has ability to inject error in any phase in a transaction
• SMBus 2.0 Master & SMBus 2.0 slave has ability to add multiple random errors in a transaction
• SMBus 2.0 monitor logs, bus traffic and generates an reports which are easy to debug from
• SMBus verification IP also includes User-configurable commands
• SMBus BFM is written in Verilog HDL and assertions in System Verilog

Product Components

• Verification Engine complaint to SMBus 2.0 specifications
• SMBus 2.0 Bus Functional Model
• Directed & Random tests generator for SMBus 2.0
• SMBus 2.0 comes bundled with a Compliance Test Suite
• System verilog assertions for SMBus 2.0
• SMBus 2.0 traffic generator comes with an Error injector with complex error injection
• Consists of SMBus 2.0 Monitor which generates detailed reports
• SMBus 2.0 master acts Transaction generator to simulate complex protocol scenarios
• Protocol Checker to log violations for SMBus 2.0 specifications

For more information on each component and evaluation copy please email to: info@perfectus.com or sales@perfectus.com