OCP Verification IP

The Perfectus VIP for OCP provides an efficient bus-independent interface between IP cores that reduces design time, design risk, and manufacturing costs for SOC designs that support Verilog HDL assertions

Highlights

• Small Set of Mandatory signals and large set of optional signals.
• Synchronous, uni-directional signaling allows simplified implementation, integration.
• Configurable address and data word width.
• Transfers may be pipelined to any depth for increased throughput

Product Component

• Verification Engine
• Bus Functional Models
• Directed & Random tests generator
• Compliance Test Suite
• Assertions
• Error injector
• Report generator
• Transaction generator
• Protocol Checker
• Protocol Monitor

For more information on each component and evaluation copy please email to: info@perfectus.com or sales@perfectus.com