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Genie-PCIe

Genie-PCIe is a system verilog implementation of the PCI Express (PCIE) Standards.

Genie PCIe

Highlights

  • Compliant with PCI Express Specification v1.0a, v1.1 and v2.0.
  • Verification IP configurable as both PCI Express Root complex and PCI Express Endpoint
  • Verification at PIPE, 10b, and serial interface.
  • PCIe Link width support: x1, x2, x4, x8, x12, x16, x32
  • Polarity inversion
  • 8-bit or 16-bit PIPE support
  • Automatic/User configurable handling of all PCI Express layer packets namely Transaction Layer, Data Link Layer and Physical Layer packets
  • PCI Express Verification IP supports upto 8 virtual channels
  • Full LTSSM (Link Training & Status) support for PCI Express verification component
  • Automatic/User configurable generation of flow control packets
  • Automatic/User configurable PCI Express credit management
  • Provides read and write transfers to memory, I/O, and configuration space
  • PCI Express VIP supports Error Injection at all layers.
  • Test suites include the PCI-SIG-based compliance tests in addition to Perfectus-based endpoint, root complex test-suites that target high compliance coverage from their corresponding checklists.
  • Tests are self-checking, portable, and reusable on most types of designs
  • PCI Express BFM generates block read and write transfers to memory space
  • PCI Express BFM also generates message transfer

Product Components

  • PCI Express based Verification Engine
  • PCI Express gen 2 complaint Bus Functional Models
  • Directed & Random tests generator
  • PCI Express Compliance Test Suite
  • Assertions
  • Error injector
  • Report generator
  • Transaction generator
  • PCI Express Protocol Checker
  • PCI Express Protocol Monitor
  • Scoreboard

For more information on each component and evaluation copy please email to: info@perfectus.com

  2007 Perfectus Technology Inc.